元器件交易网关于74HC595相关的资料

　　The MC74HC595A consists of an 8–bit shift register and an 8–bit D–type latch with three–state parallel outputs. The shift register accepts serial data74HC595 and provides a serial output. The shift register also provides parallel data to the 8–bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register74HC595. The HC595A directly interfaces with the 74HC595 serial data port on CMOS MPUs and MCUs.

　　• Output Drive Capability: 15 LSTTL Loads

　　• Outputs Directly Interface to CMOS, NMOS, and TTL

　　• Operating Voltage Range: 2.0 to 6.0 V

　　• Low Input Current: 1.0 mA

　　• High Noise Immunity Characteristic of CMOS Devices

　　• In Compliance with the Requirements Defined by JEDEC Standard

　　• Chip Complexity: 328 FETs or 82 Equivalent Gates

　　• Improvements over HC595

　　— Improved Propagation Delays

　　— 50% Lower Quiescent Power

　　— Improved Input Noise and Latchup Immunity