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单片3D集成电路将代替节点缩放促进半导体行业增长

单片3D集成电路将代替节点缩放促进半导体行业增长0

元器件交易网讯 12月18日消息,据外媒EETasia报道,集成电路缩放成本不断攀升,单片3D集成电路技术将成为维护行业增长势头开辟了新路径。

据一份Solid State Technology(固态技术)网站的报告描述,单片3D集成电路势头正紧。超过28nm制程的立体缩放成本大量增加,这点已经从高通、博通、英伟达、AMD等公司的大量报告中证实。业界正在适应这一现实,并仍为其不断攀升的成本和复杂性增加投入,开发和试用先进节点。

因此,行业为有助于维护行业整体气势的其他技术敞开了大门,如单片3D集成电路。

正如今年早些时候报道的那样,3D NAND是业界第一款采用这种新路径的产品。几个月后我们了解到BeSang公司与海力士签署单片3D技术许可协议,这可能有助于海力士提供更多有竞争力的3D DRAM(动态随机存储器)。接下来我们听说新加坡MIT联盟技术研究部门已经开发了结合集成硅CMOS及化合物半导体电动车组自动化生产系统,保证新的集成电路能支持无线设备及能源电子。上周CEA-Leti宣布就评估Leti的非TSV 3D工艺与高通公司达成协议。

这就解释了为什么Leti的演讲展示了今年IEDM2013(国际电子设备大会International ElectronDevices Meeting)促进单片3D集成电路技术代替二维技术。

单片3D集成电路将代替节点缩放促进半导体行业增长1

在Leti的这张幻灯片中可以看出单片3D技术被定位为一个更好的保持行业发展势头的路径,并提供了缩放技术无法再提供的缩减成本能力。此外单片3D技术还实现了远远降低了工厂基础设施和工艺研发的经费。幻灯片将其概括为:“每个节点不再缩小但使其增益”,其他人可能将其称为“缩放的新形式”。

单片3D集成电路将代替节点缩放促进半导体行业增长2

单片3D的基础层可能是SOI(绝缘硅)或散装,但上层很自然的是SOI。因此基于SOI的传统IEEE(电气与电子工程师协会)会议已经扩大其范围,现在被称为S3S:SOI、三维集成(3D Integration)、亚阀值微电子(Subthreshold Microelectronics)。亚阀值微电子目前状况良好,今年鲍勃·布洛德森(Bob Brodersen)在今年的会谈上提到过多次,他说:“增加晶体管(缩放、3D集成)数量是最重要的技术要求。”(元器件交易网毛毛 译)

以下为原文:

Monolithic 3D ICs gain momentum

A recent report on the Solid StateTechnology website has described how momentum is building for monolithic 3DICs. Dimensional scaling is clearly not providing transistor cost reductionbeyond the 28nm process node, as has been recently confirmed by reports fromthe large fabless companies such as Qualcomm, Broadcom, Nvidia and AMD. Theindustry is trying to accommodate this new reality, while still rushing todevelop and adopt more advanced nodes at escalating costs and complexity.

Consequently, the door has started to openfor other kinds of technology that might help to maintain the industry'soverall momentum, and monolithic 3D ICs seem well positioned to do so.

As was reported earlier this year, 3D NANDis the first segment of the industry to adopt this new path for scaling. A fewmonths later we learned that BeSang signed a license agreement with SK Hynixfor its monolithic 3D technology, which might help Hynix to offer morecompetitive 3D DRAM. Then we heard that the Singapore-MIT Alliance for ResearchTechnology has ordered EV Group automated production bonding systems forintegrating silicon CMOS and compound semiconductor materials to enable newintegrated circuits for wireless devices and power electronics. And just last week,CEA Leti announced an agreement with Qualcomm to Evaluate Leti's Non-TSV 3Dprocess.

This explains why Leti's presentation eventperformed in conjunction with this year's IEDM 2013 features slides promotingmonolithic 3D technology as an alternative to dimensional scaling; for example,consider the following slide:

Leti's presentation goes even further. Inthe following Leti slide, one can see that monolithic 3D technology ispositioned as a far better path to maintain the industry's momentum and offersthe cost reduction that dimensional scaling no longer provides. Furthermore,monolithic 3D technology also achieves this with far less costly fabinfrastructure and process R&D. As the slide sums it up: "1 node gainwithout scaling," or as others may say, "The new form of scaling isscaling up."

In monolithic 3D the base stratum might beSOI or bulk, but the upper strata are naturally SOI. It is therefore fittingthat the traditional IEEE conference on SOI has extended its scope and nowcalls itself S3S: SOI technology, 3D Integration and SubthresholdMicroelectronics. The Subthreshold section fits well, as was presented in thisyear's plenary talk by Bob Brodersen, who said "The most importanttechnology requirement is to continue the increase in the number of transistors(feature scaling, 3D integration, etc.)."

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