麻省理工学院将InGaAs整合到22nm工艺中

　　<元器件交易网>元器件讯 据外媒称，本周在旧金山召开的国际电子器件会议上麻省理工学院的研究人员展示了铟砷化镓晶体管（InGaAs），并称在22-nm工艺设计中整合III-V晶体管将会变成现实。

         铟砷化镓(InGaAs)是一种材料，主要应用于电子半导体领域。电子在InGaAs中的传输速度是硅的数倍。用InGaAs制作的晶体管被广泛用于探测器，其优点是能够减少光明尺寸，提高信息处理的速度。

　　从2009年，英特尔就在为III-V晶体管通道调整高 k金属栅堆，而丰桥技术科学大学在去年声称已经解决了在硅衬底上沉淀砷化镓的晶格失配问题。

　　麻省理工学院展示了一个铟砷化镓晶体管并称它能压缩到比硅的尺寸更小。研究人员表示他们在麻省理工学院微系统技术实验室研发的22nm晶体管证明了其在替代硅方面有很strong的前景。

　　为了构建和传统CMOS晶体管一样的芯片体系架构，研究人员用自动校准技术来制作纳米级栅。借助电子束外延沉淀通道，电子束光刻来形成源极和漏极然后钼被沉淀。氧化物使钼脱水并放射到表面后在顶部沉淀，中间极被蚀刻出来。

　　“借助蚀刻和沉淀的组合，我们能得到围有细小的缝隙的栅(位于源极和漏极之间)，”麻省理工学院宣称。

　　麻省理工学院的下一个目标是通过优化堆降低阻抗来改善他们的InGaAs晶体管的电子特性。这个研发团队的终极目标是生产出比硅电子传输速度更快的III-V晶体管，并将栅长度缩短到10nm。（MOSFET交易网刘光明 译） 

             外媒原文如下：

　　MIT integrates InGaAs in 22-nm design flow

　　PORTLAND, Ore. -- Integrating III-V transistors into 22-nm design flows may soon be possible, according to the Massachusetts Institute of Technology (MIT) researches who demonstrated indium-gallium arsenide (InGaAs) transistors at the International Electron Devices Meeting (IEDM) this week in San Francisco.

　　Since 2009, Intel has been tweaking high-k metal gate stacks for III-V transistor channels while Toyohashi University of Technology claimed last year to have solved the lattice mismatch in depositing gallium arsenide on silicon substrates.

　　MIT demonstrated an indium gallium arsenide transistor that it claims can be shrunk to smaller dimensions than silicon. Built by MIT’s Microsystems Technology Laboratories, the researchers claim their 22-nm demonstration transistor show that InGaAs is a promising candidate to replace silicon at advanced technology nodes.

　　Employing the same MOSFET architecture as conventional CMOS transistors, the researchers used self-aligning techniques to fabricate the nanoscale gate. Using molecular beam epitaxy to deposit the channel, molybdenum was then deposited using e-beam lithography to form the source and drain electrodes. The middle gate was then etched with oxide deposited on top after which evaporated molybdenum was fired at the surface.

　　"With a combination of etching and deposition we can get the gate nestled [between the source and drain electrodes] with tiny gaps around it," MIT said.

　　The MIT is next aiming to improve the electrical performance of their InGaAs transistor by optimizing the stack to reduce resistance. The team"s ultimate goal is to produce III-V transistors that are faster than silicon and have gate lengths as short as 10 nm.