<strong> XCF32PV0G48C Features
In-System Programmable PROMs for Configuration ofXilinx FPGAs
Low-Power Advanced CMOS NOR FLASH Process
Endurance of 20,000 Program/Erase Cycles
Operation over Full Industrial Temperature Range(-40°C to +85°C)
IEEE Standard 1149.1/1532 Boundary-Scan (JTAG)
Support for Programming, Prototyping, and Testing
JTAG Command Initiation of Standard FPGA Configuration
Cascadable for Storing Longer or Multiple Bitstreams
Dedicated Boundary-Scan (JTAG) I/O Power Supply(VCCJ)
I/O Pins Compatible with Voltage Levels Ranging From 1.5V to 3.3V
Design Support Using the Xilinx Alliance ISE and
Foundation ISE Series Software Packages
XCF32PV0G48C Description
Xilinx introduces the Platform Flash series of in-system programmable configuration PROMs. Available in 1 to 32 Megabit (Mbit) densities, these PROMs provide an easy-to-use, cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams. The Platform Flash PROM series includes both the 3.3V XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS version includes 4-Mbit, 2-Mbit, and 1-Mbit PROMs that support Master Serial and Slave Serial FPGA configuration modes (Figure 1, page 2). The XCFxxP version includes 32-Mbit, 16-Mbit, and 8-Mbit PROMs that support Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP FPGA configuration modes (Figure 2, page 2). A summary of the Platform Flash PROM family members and supported features is shown in Table 1.XCF32PV0G48C
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