<strong>XC2C32A-4VQG44C Features
Optimized for 1.8V systems
Industry’s fastest low power CPLD
Densities from 32 to 512 macrocells
Industry’s best 0.18 micron CMOS CPLD
Optimized architecture for effective logic synthesis
Multi-voltage I/O operation - 1.5V to 3.3V
Advanced system features
Fastest in system programming
1.8V ISP using IEEE 1532 (JTAG) interface
On-The-Fly Reconfiguration (OTF)
IEEE1149.1 JTAG Boundary Scan Test
Optional Schmitt trigger input (per pin)
Multiple I/O banks on all devices
Unsurpassed low power managem
XC2C32A-4VQG44C Family Overview
Xilinx CoolRunner-II CPLDs deliver the high speed and ease of use associated with the XC9500/XL/XV CPLD family with the extremely low power versatility of the XPLA3 family in a single CPLD. This means that the exact same parts can be used for high-speed data communications computing systems and leading edge portable products, with the added benefit of In System Programming. Lowpower consumption and high-speed operation are combined into a single family that is easy to use and cost effective. Clocking techniques and other power saving features extend the users’ power budget. The design features are supported starting with Xilinx ISE? 4.1i WebPACK tool. Additional details can be found in Further Reading, page 14. Table 1 shows the macrocell capacity and key timing parameters for the CoolRunner-II CPLD family. XC2C32A-4VQG44C
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