<strong>CY7C0852AV-133BBI产品特点
True dual-ported memory cells that allow simultaneous access of the same memory location
Synchronous pipelined operation
Organization of 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit devices
Pipelined output mode allows fast operation
0.18-micron CMOS for optimum speed and power
High-speed clock to data access
3.3V low power
— Active as low as 225 mA (typ)
— Standby as low as 55 mA (typ)
Mailbox function for message passing
Global master reset
Separate byte enables on both ports
Commercial and industrial temperature ranges
IEEE 1149.1-compatible JTAG boundary scan
172-ball FBGA (1 mm pitch) (15 mm × 15 mm)
176-pin TQFP (24 mm × 24 mm × 1.4 mm)
Counter wrap around control
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
Counter readback on address lines
Mask register readback on address lines
Dual Chip Enables on both ports for easy depth expansion
CY7C0852AV-133BBI Master Reset
The FLEx36 family devices undergo a complete reset by taking its MRST input LOW. The MRST input can switch asynchronously to the clocks. The MRST initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). The MRST also forces the Mailbox Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags HIGH. The MRST must be performed on theFLEx36 family devices after power-up.
CY7C0852AV-133BBI Address Counter and Mask Register
Operations[10]
This section describes the features only apply to CY7C0850AV/CY7C0851AV/CY7C0852AV devices, but not to the CY7C0853AV device. Each port of these devices has a programmable burst address counter. The burst counter contains three registers: a counter register, a mask register,and a mirror register.
The counter register contains the address used to access the RAM array. It is changed only by the Counter Load, Increment,Counter Reset, and by master reset (MRST) operations.The mask register value affects the Increment and Counter Reset operations by preventing the corresponding bits of the counter register from changing. It also affects the counter interrupt output (CNTINT). The mask register is changed only by th e Mask Load and Mask Reset operations, and by the MRST. The mask register defines the counting range of the counter register. It divides the counter register into two regions: zero or more “0s” in the most significant bits define the masked region, one or more “1s” in the least significant bits define the unmasked region. Bit 0 may also be “0,” masking the least significant counter bit and causing the counter to increment by two instead of one.
The mirror register is used to reload the counter register on increment operations (see “retransmit,” below). It always contains the value last loaded into the counter register, and is changed only by the Counter Load, and Counter Reset opera-tions, and by the MRST.Table 3 summarizes the operation of these registers and the required input control signals. The MRST control signal is asynchronous. All the other control signals in Table 3 (CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the port’s CLK. All these counter and mask operations are independent of the port’s chip enable inputs (CE0 and CE1).Counter enable (CNTEN) inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast, interleaved memory applications. A port’ s burst counter is loaded when the port’s address strobe (ADS) and CNTEN signals are LOW. When the port’s CNTEN is asserted and the ADS is deasserted, the address counter will increment on each LOW to HIGH transition of that port’s clock signal. This will Read/Write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array, and will loop back to the start. Counter reset (CNTRST) is used to reset the unmasked portion of the burst counter to 0s. A counter-mask register is used to control the counter wrap.
版权所有