国家集成电路设计成都产业化基地诚邀您参加“DFT & Digital 三环 Testing 培训班”。
时间：2003年9月11日至9月12日
地点：国家集成电路设计成都产业化基地
地址：成都市高新西区 （羊西线AMD路外四公里处）
讲师：杨梧 先生
收费：RMB 1200元/人，3人以上团体报名1000元/人，在校学生凭有效证件1000元/人 （含听课费，讲义，午餐）
讲师介绍：杨梧先生是美国攀派科技公司(PAN-PAC TECHNOLOGY)创办人，是面向芯片可测试设计应用的专家，其工作及研究领域几乎深入到芯片可测试性设计及测试的方方面面。杨先生曾数次回国在北京，上海，武汉等地举办十多次有关芯片可测试设计讲座。他原工作于美国Mentor Graphics公司可测试设计部，任职高级应用工程师多年，期间为众多世界著名芯片公司如英特尔，摩托罗拉，LSI，ST 等提供各项可测试设计技术支持服务。之后，他出任美国泰赛达(测试机研发)公司顾问并继任测试机核心研发部高级质量师/内部高级应用工程师。他本科毕业于南京航空航天大学电子工程系，后获美国波特兰州立大学电子与计算机工程科学硕士学位。IEEE会员。
课程介绍:
IC testing cost has been continuously high in the IC manufacturing. A lot of people have come up great ideas to bring down the cost by reducing the ATE expenses, simplifying functional patterns and adopting efficient processes, etc. One of the hot topics, Design for Test (DFT), is to consider the testability as early as the IC design stage, automates the pattern generation, facilitates the diagnosis and shortens time-to-market and time-to-yield.
This seminar focuses on the DFT techniques, the application and its role in the IC testing flow. On the other hand, it talks about the test components and looks at IC testing from the ATE point of view. Finally it talks about engineering debugging on DFT structured device.
SCHEDULE:
This seminar will take about one and half days. Proposed schedule will be Sep. 11th and 12th of 2003.
AUDIENCE:
Digital IC designers, Testing Engineers, Production Engineers, IC Application engineers, Managers who are interested in the IC testing flow and cost estimation and reduction, EE students and IC testing Technicians.
Prerequisite: Having electrical & electronics backgrounds. EE students recommend to be in their senior years or above.
OUTLINES
Testing Components: That’s All You Have To Do In Testing
Briefly speaking, they consist of internal tests, which are normally DFT oriented, functional tests, parametric tests and environment tests. This section is going to talk about what they are and how they impact your testing life.
ATE & IC Testing: Too Expensive to Ignore It
What cause ATEs expensive are the precision, speed, memory, channels and integration of digital and analog test functionalities. What do the ATE specs mean to you? Topics include waveforms, strobes, PMU, cost estimation, breakeven point calculation, etc. How they associate with IC testing. Availability and specifications of ATEs limit your design flow, test strategy and time-to-market.
Trend in ATE: structural tester, low cost tester. What they do and how they reduce your cost.
Traditional Testing: TIre Challenges And Expensive
Event driven and cycle based tests. How people develop the functional patterns for digital IC: verilog testbench to VCD. Advantages and disadvantages of functional tests. ATEs and functional tests. What are parametric tests? Open/short tests. IDD Test. Output voltage testing. Input leakage testing, Tristate leakage test. Wafer sorting. Testing Pies (overlap of different type of patterns detecting faults).
Test Economics: My Managers’ Jobs
Moore’s cycle. Test preparation (DFT logics, test-related silicon., pattern generation, pattern simulation, and tester program generation). Test execution (DUT card design, probe cards, temperature generator, handler, drier, production test time, IC debugging, ATE cost). Test escape cost. Defect level (Yield loss vs Test coverage). Diagnosis, Failure analysis. Cost of failure at different stages. Time-to-market, time-to-yield. Test cycle (test time) calculation. Test economics drives DFT technology, low cost DFT oriented tester and standard test program.
DFT Technology
--Scan and Faults: Cornerstone Of DFT technology
Common scan types. Scan variations. How scan work? Scan in ATPG. Scan in BIIC. Scan in Boundary scan. DC scan, AC scan (LOS, LOC). How defects are modeled? Fault types.
--Test Synthesis: Key To High Test Coverage And Design Penalty
Scan insertion. Partial scan, full scan. Scan assembly, chain balance, lockup latch placement. Dealing with the multiple phase clocks. Bottom up and top down test synthesis. How to deal with multiple types of scan cells. Test Synthesis rules.
-- DRC rules: The Bridges To Success
Clock rules, bus (bidi) rules, AVI rules, data traction rules, memory test rules, scan tracing rules.
--ATPG and Pattern generation: Let Machine Do It??
ATPG algorithm. Procedures. True beauty of fault simulation. How to fault simulation functional patterns in ATPG? Bus contention in pattern generation. Abort limit. Sequential ATPG.
Pre-shift, post-shift, end-measurement. Strobe edges: where do I put them (give out an example)
Fault collapsing. Why ATPG untestable, why DI, UU, Mo, BL, RE etc. What’s the atpg effectiveness? What’s the test coverage and fault coverage? How do you calculate the test coverage? How to increase the test coverage? On chip PLL testing (new method in ac scan). Z masking, padding. Scan cell mask, outputs mask in transition faults.
--BIST: Pros And Cons
Memory faults. Memory testing methods. Embedded memory testing, at-speed memory testing. Logic BIST structural, the benefits and the penalty. LBIST flow: phase shift, PRPG, MISR, x-bounding. At-speed logic BIST. ATPG top-up in logic BIST design.
--Boundary Scan: Don’t Think It’s Too Simple
Structure of Boundary scan. Can control Memory BIST, LBIST, ATPG (state machine analysis plus an example). Can do board testing (JTAG technology, Asset International). An example on atpg through boundary scan.
--Pattern Optimization and Technology: Great Area to Hammer DFT
Pattern compression during ATPG. Pattern ordering. EDT technology, DBIST, XDBIST (deterministic BIST). Macro pattern, fault simulation. Transition pattern generation to iddq pattern generation.
--Diagnosis: Did I Really Do Something Wrong?
Scan logs. How many failed patterns you need to do diagnosis? What does the values mean in fault simulation and good simulation values. Memory BIST diagnosis. LBIST diagnosis: the difficult thing. How to correlate the pattern with signature?
--IDDQ pattern generation and Analysis: This Is Analog!?
IDDQ analysis. How leakage current estimated. Pull up, pull down in IDDQ pattern generation. Tristate in iddq pattern generation. How to efficiently generate IDDQ pattern. Delta IDDQ. Delta IDDQ in wafer sorting.
Engineering IC Debugging: DFT Engineers Hate It
DC conductivity. Chain tests: diagonal chain pattern. Edge adjustments. Timing factor. DC, scan debugging. AC scan debugging. IDDQ debugging. Shmooing, strobe, clock edge, power supply setup. Two dimension shmooing. Three dimension shmooing. Clock dependency. Flaky results (an example scan chain debugging). Power on order. Probe clk, probe scan-enable. Setting up trigger. Calibration. Pattern qualification, verification.
DFT & Digital IC Testing 培训班 回执
请于2003年9月3日前将此回执传真至028－87826170（联系人：齐静静），我们会为您预留座位。
贵公司全称：___________________________________________________________
参加人数：_________人
付款方式： □ 现金
□ 转帐 （开户单位：成都集成电路设计产业化基地有限公司
开户银行：成都市商业银行德盛支行
帐 号：2901 2009 2104 0880 0017）
参加人：
您的姓名：_______________________ 性别：□男 □女
所在部门：________________ 职务：______________ E-mail:________________________
电 话：__________________________________ 传真：__________________________
是否需安排住宿：□是 □否
参加人：
您的姓名：_______________________ 性别：□男 □女
所在部门：________________ 职务：______________ E-mail:________________________
电话：__________________________________ 传真：__________________________
是否需安排住宿：□是 □否
参加人：
您的姓名：_______________________ 性别：□男 □女
所在部门：________________ 职务：______________ E-mail:________________________
电话：__________________________________ 传真：__________________________
是否需安排住宿：□是 □否
版权所有